Design Verification Engineer

Description:

This challenging position offers the Digital Verification Engineer the opportunity to work with leading edge sensor technologies embedded in smartphones, automotive, IOT, smartwatches as well as other consumer electronics devices. Job activities span the ASIC design verification process from test planning, environment development using UVM, regressions, coverage analysis and meeting all company quality metrics for tapeout.

This friendly Irish location offers an ideal mix of vibrant city life close to peaceful countryside and sweeping coastlines. There is something for everyone, with excellent amenities for families, many cultural events and festivals throughout the year, and a great culinary and music scene.

A very competitive basic salary, together with bonus, stock, and a generous benefits scheme including a good pension package and medical insurance. My client will provide relocation assistance to help you move and settle in.

For this Verification role you will need:

• ASIC design verification, UVM-based functional verification, or related work experience.
• Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology
• Experienced with Assertions like System Verilog Assertions
• Experience with debugging test failures and report verification result
• UVM, System Verilog, Perl/Python shell-scripting skills required
• Familiarity with C/C++