Description:
A well-funded, fast-growing Semiconductor company with offices in Paris, Grenoble, and Caen looking for a technical leader in DFT to lead their team remotely in Europe.
In this role, you'll be instrumental in shaping the Design for Test (DfT) strategy. You'll help define and execute DfT activities across multiple sites, ensuring deliverables meet expectations. You will play a key leadership role in building, motivating, and developing a talented DfT team.
Responsibilities:
- Spearhead all Design for Test (DFT) initiatives for all circuits, working closely with the R&D Development Director.
- Mentor and empower the DFT team(s), collaborating with technical and development leadership.
- Own the design flow methodology, including DFT integration, static timing analysis, test vector generation, and validation.
- Implement Design Rule Checks (DRC) using SPYGLASS in RTL and create DFT design constraints.
- Analyze DFT metrics and proposed solutions to optimize yield, test coverage, and test time across wafers, packages, and operation.
- Collaborate seamlessly with Front-End (FE) design and Back-End Digital teams to ensure minimal impact on circuit Power, Performance, and Area (PPA) during DFT insertion.
- Perform static timing analysis for all test logic at the physical partition and top levels.
- Orchestrate the production launch of multiple circuits annually.
Qualifications and Experience:
- DFT Leadership: Drive high visibility internally and externally by defining and implementing robust DFT architectures for complex SoCs.
- Proven Expertise: Possess 10+ years of experience in DFT, ensuring a deep understanding of the field.
- Complex Chip Experience: Demonstrated ability to define DFT architectures and plan stages for complex circuits
- Advanced DFT Techniques: Utilize extensive experience with Scan/EDT/SSN, Logic BIST, MBIST, ATPG, and Boundary Scan on large, complex circuits.
- Scripting Proficiency: Leverage strong skills in scripting languages like Pearl, TCL, or Python for efficient automation tasks.
- Solid Design Foundation: Possess a strong foundation in logic synthesis and static timing analysis, crucial for effective DFT implementation.