Senior Verification Engineer

Description:

Are you an experienced Senior Verification Engineer looking for your next challenge? We are working with a leading technology innovator seeking a skilled professional to join their team.

There are opportunities within multiple teams across diverse product lines, including IoT, Mobile, Automotive, XR, and Compute, all focused on enabling embedded processing solutions If you’re passionate about solving complex problems and want to be part of a diverse, multicultural environment, this opportunity is for you!

Key Responsibilities
 

• Develop verification methodologies such as UVM and Formal Verification.
• Develop testbenches and verification components.
• Develop test plans based on design documents and collaborate with design/systems engineers.
• Integrate C models within a UVM framework.
• Write SystemVerilog assertions and debug, verify, and optimise test vectors.
• Automate workflows and improve team efficiency using Python.
• Collaborate with cross-functional teams, including design, SoC, and validation teams, to solve problems at various levels.
   

Key Skills
 

• Experience in ASIC design verification.
• Strong experience with UVM and SystemVerilog.
• Familiarity with formal verification is a plus.
• Understanding of processor/microcontroller sub-systems is advantageous.
• Proficiency in power-aware verification methodologies.
• Expertise in constrained-random verification environments and coverage-driven methodologies.
• Familiarity with System Verilog assertions.
• Familiarity with C/C++.